Although introduced over thirty years ago, the TTL (transistor-transistor logic) integrated logic standard fabricated in an npn bipolar process is still widely used as an interface in current CMOS digital systems. Bipolar circuits have the particular advantage of being able to operate at the high speeds that are required in current telecommunications transmission systems. These TTL circuits have a standard `totem pole` output stage comprising a series connected pair of transistors providing a respective pull-up and pull-down stage. Although low voltage excursion is achievable from the pull-down stage, the high voltage excursion of the pull-up stage is limited by the supply voltage that is applied to the circuit. At best, the high voltage output is limited to a value equal to the positive supply voltage less the sum of the base-emitter voltages (Vbe.sub.ON) of the two output transistors in their conductive state. The magnitude of the voltage Vbe.sub.ON is determined by current density and temperature, but is generally between 0-6 and 1.0 volts. In the past, the effect of the value of Vbe.sub.ON on the output voltage has not been a significant problem as it is relatively small in comparison with the standard circuit supply voltages of 12 volts and 5 volts. However newer CMOS designs having a supply voltage of only 3.3 volts are now being introduced. With such a low supply voltage, the output of a conventional TTL output stage falls below the 2-4 volts that is required for adequate circuit performance.
A possible solution to this problem is the provision of an additional power supply for the TTL circuitry. This however is generally inconvenient both in terms of added complexity and increased cost.